Design of an accurate NoC for Multiprocessor SoC

Any integrated system consists of a host processor, memory and peripheral elements which are interconnected through a bus interface. The synchronization of these basic blocks with internal and external environment is achieved by means of an I/O buffer. The work is intended to develop a self-reconfigurable channel data buffering form and circuit design for network-on-chips (NoCs). The design is optimized for power efficiency and data throughput, from system to circuit level. The adaptive flow control enables to control the congestion by reconfiguration of channel through adaptive techniques. Here we design a NoC on a SoC to meet the electrical specifications dictated by industry standards.